10/16(三)碩博論文研討─資訊系統與系統設計(英)，演講資料如下，歡迎蒞臨！
時間：10月16日 星期三 13:20~15:10
地點：工程三館 114教室
演講者：陳呈瑋博士 (Dr. ChengWei Chen)，聯發科技 經理
講題：Heterogeneous System Architecture, Its Intermediate Layer,
and Linking Support
and Linking Support
摘要：
It is widely agreed that the future of computing will be heterogeneous. The CPU
and GPU are the two major components in the SoC of smart devices. Heterogeneous
System Architecture (HSA) defines a standard for parallel programming on the
heterogeneous processing units. HSA is possible to fundamentally change the way
that people program heterogeneous devices.
In this talk, the recent development and technology concept of HSA will be introduced.
The HSA Intermediate Layer, a virtual ISA for parallel programs will be illustrated as well.
With HSA's shared virtual memory, we will describe the recent discussion regarding the
linking support for accessing global variables across processing units in HSA.
經歷：
ChengWei Chen is a senior manager of Compiler Infrastructure Technology in the
Corporate Technology Office of MediaTek Inc since 2011. He is currently the lead of
several compiler projects, which aim at providing a compilation infrastructure for high
performance heterogeneous computing on embedded platforms.
Prior to joining in MediaTek, he was with Marvell from 2005 to 2011, and he was a
manager in charge of building a compiler team in Taiwan from scratch for Marvell ARM
superscalar processors. He worked at IC Design Technology Center,
National Tsing Hua University from 2002 to 2004, where he was a postdoctoral
researcher in retargeting the ORC (Open64) compiler to PAC VLIW DSP by SoC
Technology Center, ITRI.
He received his B.S. degree in computer science and information engineering from
Yuan Ze University in 1995. He received his M.S. and Ph.D. degrees in computer science
from National Tsing Hua University in 1997 and 2002, respectively. In 2009 he served as
an adjunct assistant professor at Dept. of Computer Science & Information Engineering,
National Taiwan University of Science & Technology, where he was a co-instructor of
compiler design. His primary research interests include compiler optimization, microprocessor
architecture and performance exploration, program analysis, virtual machine with JIT
compilation, and library optimization for specific ISA.