很榮幸邀請到Joseph R. Cavallaro前來交通大學資工系演講,演講題目與摘要如下所示,歡迎同學前往聆聽與交流,感謝大家的參與！

此次活動特別邀請到Center for Multimedia Communication, Dept. of Electrical and Computer Engineering, Rice University, USA的Joseph R. Cavallaro前來為我們演說「Advances in Wireless Communication Systems for the Internet of Things: Algorithms, Architectures, and Testbeds」議題，歡迎有興趣的老師與同學免費參加！

Advances in Wireless Communication Systems for the Internet of Things: Algorithms, Architectures, and Testbeds

一、演講時間：2019/10/17 (四) 10：10 - 12：00

二、演講地點：工程三館411教室

三、講    者：Joseph R. Cavallaro, Center for Multimedia Communication, Dept. of Electrical and Computer Engineering, Rice University, Houston, TX, USA

四、演講摘要：

Wireless communication system concepts for beyond 5G include a variety of advanced physical layer algorithms to provide high data rates and increased efficiency for emerging Smart City and Internet of Things devices.  All of these wireless algorithms provide different challenges for real-time performance based on the tradeoffs between computation, communication, and I/O bottlenecks and area, time, and power complexity.  In particular, proposed large scale or Massive MIMO systems can provide many benefits for both uplink detection and downlink beamforming as the number of base station antennas increases.  Similarly for error protection, channel coding, such as LDPC, can support high data rates in many channel conditions.  At the radio frequency level, limited available spectrum is leading to noncontiguous channel allocations where digital pre-distortion (DPD) can be used to improve power amplifier efficiency and transmission range.  Each of these schemes impose complex system organization challenges in the interconnection of multiple RF transceivers with multiple memory and computation units with multiple data rates within the system.  Parallel numerical methods can be applied to tradeoff computational complexity with minimal effect on error rate performance.  Simulation acceleration environments can be used to provide thorough system performance analysis.  In this talk, we will focus on design tools for high level synthesis (HLS) to capture and express parallelism in wireless communication algorithms.  This also includes the mapping to GPU and multicore systems for high speed simulation.  HLS can also be applied to FPGA and ASIC synthesis, however, there exist tradeoffs in the area required with flexibility and reuse of designs.  Heterogeneous system architectures as expressed by Systems on Chip (SoC) attempt to address these system issues.  The talk will conclude with a discussion of computation testbeds from supercomputers through desktop GPU to single board systems.  The integration with radio testbeds from WARP and USRP to NI and Argos prototype massive MIMO systems will be explored.  This includes the new National Science Foundation Platforms for Advanced Wireless Research (PAWR) collaboration between universities and industry and the POWDER-RENEW and COSMOS testbeds.

五、講者簡歷：

Joseph R. Cavallaro (S'78, M'82, SM’05, F’15) received the B.S. degree from the University of Pennsylvania, Philadelphia, PA, in 1981, the M.S. degree from Princeton University, Princeton, NJ, in 1982, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1988, all in electrical engineering. He is an IEEE Fellow. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, TX, where he is currently a Professor of electrical and computer engineering and Associate Chair. His research interests include computer arithmetic, and DSP, GPU, FPGA, and VLSI architectures for applications in wireless communications. During the 1996–1997 academic year, he served at the US National Science Foundation as Director of the Prototyping Tools and Methodology Program. He was a Nokia Foundation Fellow and a Visiting Professor at the University of Oulu, Finland in 2005 and continues his affiliation there as an Adjunct Professor. He is currently the Director of the Center for Multimedia Communication at Rice University. He is an advisory board member of the IEEE SPS TC on Design and Implementation of Signal Processing Systems and the Chair of the IEEE CAS TC on Circuits and Systems for Communications. He was an Associate Editor of the IEEE Transactions on Signal Processing and the IEEE Signal Processing Letters, and currently serves as an AE for the Journal of Signal Processing Systems. He was General/Program Co-chair of the 2003, 2004, and 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), and General/Program Co-chair for the 2012, 2014 ACM/IEEE GLSVLSI conferences. At the IEEE SiPS workshop, he was TPC Co-Chair in 2016 and General Co-Chair in 2020. At the IEEE Asilomar Conference on Signals, Systems, and Computers, he was TPC Chair in 2017 and General Chair in 2020. He served on the IEEE CAS Society Board of Governors during 2014.

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