陳添福 Tien-Fu Chen 教授

Tien-Fu Chen received the B.S. degree in Computer Science from National Taiwan University in 1983. After completed his military services, he joined Wang Computer Ltd., Taiwan as a software engineer for three years. He was in charge of designing Wang operating system kernel. From 1988 to 1993 he attended the University of Washington, receiving the M.S. degree and Ph.D. degrees in Computer Science and Engineering in 1991 and 1993 respectively. He is currently a Professor in the Department of Computer Science and Information Engineering at the National Chung Cheng University, Chiayi, Taiwan. His current research interests are System Architectures, System-on-Chip Design, and Embedded Software Systems.

In past years, he had published several widely-cited papers on dynamic hardware prefetching architectures and designs. In recent years, he has made contributions to processor design and SOC design methodology. He was actively involved in the design of 8-bit CISC/RISC microcontrollers and also the CCU32 Project, which builds a 32-bit RISC processor core, low-power architecture techniques as well as related support tools and verification environment. The 32-bit processor IP implementation has been used in industrial products. In recent years, he is focusing on building multithreading multicore processors and their SOC platform. His current research is actively in developing a brand-new VLIW high-end processor, called UniCoreR (unified RISC/DSP processors). The new design is expected to be the first innovative embedded processor in Taiwan academia. 　

To make solid background in SOC, he thoroughly studied and rework the embedded Linux and real-time kernel as a target for Linux on chip. He proposed an event-driven threading system architecture, which may solve the scalability problems in embedded networking servers. The work flourished an embedded proxy system server, which has been transferred to an industry company. The throughout experience from embedded systems to VLSI processor design makes him more solid in the research of software/hardware codesign and related system issues for SOC design. His core knowledge and experience in system implementations have earned him the distinction of being able to closely collaborate with hardware and software colleagues as well as to glue several teamwork projects.

1. Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam”A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications” J. Solid-State Circuits 52(1): 218-228 (2017)
2. Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Yen-Ning Chiang, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu”A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing” J. Solid-State Circuits 52(6): 1664-1679 (2017)
3. Keng-Hao Yang, Hsiang-Jen Tsai, Chia-Yin Li, Paul Jendra, Meng-Fan Chang, Tien-Fu Chen”eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache” IEEE Trans. on Circuits and Systems 64-I(4): 858-868 (2017)
4. Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen”Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control” ACM Trans. Design Autom. Electr. Syst. 22(3): 46:1-46:27 (2017)
5. Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen”Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology” IEEE Trans. VLSI Syst. 25(3): 962-973 (2017)
6. Hsiang-Jen Tsai, Chien-Chih Chen, Yin-Chi Peng, Ya-Han Tsao, Yen-Ning Chiang, Wei-Cheng Zhao, Meng-Fan Chang, Tien-Fu Chen”A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata” IEEE Trans. VLSI Syst. 25(12): 3302-3316 (2017)
7. Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen”ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures“ IEEE Trans. VLSI Syst. 25(12): 3341-3354 (2017)
8. TF Chen, MF Chang, KH Yang” Tag memory and cache system with automating tag comparison mechanism and cache method thereof”,US Patent App. 15/163,682
9.PH Wang, TF Chen,” Reducing Timing Discrepancy for Energy-Efficient On-Chip Memory Architectures at Low-Voltage Mode”,Smart Sensors at the IoT Frontier, 73-106
10. Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew Brightsky, Sangbum Kim, Hsiang-Lan Lung, Chung Lam” A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications”, IEEE Journal of Solid-State Circuits 52 (1), 218-228(2017)
11. Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen”Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors”. Integration 54: 24-36 (2016)
12. Meng-Fan Chang, Li-Yue Huang, Wen-Zhang Lin, Yen-Ning Chiang, Chia-Chen Kuo, Ching-Hao Chuang, Keng-Hao Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu”
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing.” J. Solid-State Circuits 51(11): 2786-2798 (2016)
13. Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen”Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.” IEEE Trans. on Circuits and Systems 63-II(10): 969-973 (2016)
14.TY Shyu, BY Su, TJ Lin, C Yeh, JS Wang, TF Chen,” Variable-length VLIW encoding for code size reduction in embedded processors”, System-on-Chip Conference (SOCC), 2016 29th IEEE International, 296-299
15. Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen”High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. “IEEE Trans. VLSI Syst. 24(3): 1169-1173 (2016)
16.Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam “7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.” ISSCC 2016: 134-135
17. Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang”7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell.” ISSCC 2016: 136-137

更多著作資訊：
http://scholar.google.com/citations?hl=en&user=coZE3XcAAAAJ&sortby=pubdate&view_op=list_works

1. 打造工業物聯網WISE-PaaS教材設計(2018/02/12~2018/12/31)，研華股份有限公司
2. 107年度「聯發科技-交大創新研究中心」研究計畫書-「計算平台技術」(2018/01/01 ~ 2018/12/31)，聯發科技股份有限公司
3. 實現深度學習於產業服務之邊端智慧系統架構與其設計流程(1/4)( 2018/01/01 ~ 2018/12/31)，科技部
4. 國立交通大學物聯網智慧系統研究中心(四)PaaS Lab (2018/01/01~2018/12/31)，研華股份有限公司
5. 產業用物聯網基礎技術: 大規模資料收集分析平台與產業智慧PaaS系統(3/4) (2017/10/01 ~ 2018/09/30)，科技部/研華股份有限公司
6. 應用於產業物聯網之智慧學習垂直整合系統與架構研究(2017/08/01~2018/01/21)，科技部
7. 光寶與交大合作案─以資料分析與機器學習為運算負載之伺服器在SSD及NVMe使用分析研究( 2017/01/01 ~ 2018/12/31)，光寶科技股份有限公司
8. 106年度「聯發科技-交大創新研究中心」研究計畫書-「計算平台技術」(2017/01/01 ~ 2017/12/31)，聯發科技股份有限公司
9. 國立交通大學物聯網智慧系統研究中心(三)PaaS Lab (2017/01/01~2017/12/31)，研華股份有限公司
10. 應用於工業物聯網之超低電壓末端元件及邊端計算系統設計關鍵技術-子計畫三：超低功耗終端記憶體架構及邊端計算閘道系統設計(2016/08/01~2017/12/31)，科技部
11. 產業用物聯網基礎技術: 大規模資料收集分析平台與產業智慧PaaS系統(2/4)(2016/10/01~201711/30)，科技部/研華股份有限公司
12. 應用於工業物聯網之超低電壓末端元件及邊端計算系統設計關鍵技術-子計畫三：超低功耗終端記憶體架構及邊端計算閘道系統設計(2016/08/01~2017/12/31)
13. 結合非揮發性之多核心系統與記憶體架構(2014/08/01~2017/10/31)，科技部
14. UDVS Memory Subsystem & Vision Processing SoC Virtual Platform(2013/08/01 ～ 2016/07/31)，國科會