Publications, Talks, and Activities

Journal Articles

[J13] Chia-Heng Yen, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, and Mango Chao, "CNN-based Stochastic Regression for IDDQ Outlier Identification," in preparation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J12] Wei-Tao Huang, Li-An Huang, and Kai-Chiang Wu, "Cost-Effective Timing Speculation for In-Situ Aging Resilience," submitted to ACM Transactions on Design Automation of Electronic Systems.

[J11] Tsung-Kai Su, Wei-Kai Cheng, Cheng-Yueh Chen, Wei-Chun Wang, Yung-Tang Chuang, Guang-Hsun Tan, Hao-Cheng Lin, Cheng-Hung Hou, Ching-Min Liu, Ya-Chu Chang, Jing-Jong Shyue, Kai-Chiang Wu, and Hao-Wu Lin, "Room-Temperature Fabricated Multilevel Non-Volatile Lead-Free Cesium Halide Memristors for Reconfigurable In-Memory Computing," accepted and in press, ACS Nano.

[J10] Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, and Mango Chao, "Methodology of Generating Timing-Slack-Based Cell-Aware Tests," accepted and in press, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J09] Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi-Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, and Mango Chao, "Test Methodology for Defect-based Bridge Faults," IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 7, pp. 975-988, July 2022.

[J08] Ning-Chi Huang, Chao-Wei Cheng, and Kai-Chiang Wu, "Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs," IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 1, pp. 81-94, Jan. 2022.

[J07] Li-Wei Chen, Wei-Chun Wang, Shao-Han Ko, Chien-Yu Chen, Chih-Ting Hsu, Fu-Ching Chiao, Tse-Wei Chen, Kai-Chiang Wu, and Hao-Wu Lin, "Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing," Advanced Intelligent Systems, vol. 3, no. 1, pp. 1-11, Jan. 2021.

[J06] Tien-Hung Tseng, Chung-Han Chou, and Kai-Chiang Wu, "Making Aging Useful by Recycling Aging-Induced Clock Skew," ACM Transactions on Design Automation of Electronic Systems, vol. 25, no. 2, pp. 1-24, March 2020.

[J05] Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, and Shih-Chieh Chang, "Sensor-Based Time Speculation in the Presence of Timing Variability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 6, pp. 1133-1142, June 2018.

[J04] Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, and Shuen-Shiang Yang, "BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 10, pp. 1591-1595, Oct. 2014.

[J03] Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, and Kai-Chiang Wu, "NBTI and Leakage Reduction Using ILP-Based Approach," IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 9, pp. 2034-2038, Sep. 2014.

[J02] Kai-Chiang Wu and Diana Marculescu, "Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment," IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 1, pp. 136-145, Jan. 2014.

[J01] Kai-Chiang Wu and Diana Marculescu, "A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits," IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 2, pp. 367-379, Feb. 2013.

Conference Papers

[C34] Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, and Mango Chao, "Rule Generation for Classifying SLT Failed Parts," in Proc. of VLSI Test Symposium (VTS), pp. 1-7, April 2022. (Acceptance rate = ??%)

[C33] Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu*, and Mango Chao, "Improving Cell-Aware Test for Intra-Cell Short Defects," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 436-441, March 2022. (Regular Paper, Acceptance rate = 25%)

[C32] Kai-Chiang Wu et al., "FOX-NAS: Fast, On-device and Explainable Neural Architecture Search," in Proc. of Int'l Conference on Computer Vision (ICCV) Workshop on Low-Power Computer Vision, pp. 789-797, Oct. 2021.

[C31] Kai-Chiang Wu et al., "The 2020 Low-Power Computer Vision Challenge," in Proc. of Int'l Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 1-4, June 2021.

[C30] Shu-Ming Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, and Kai-Chiang Wu, "ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design," in Proc. of Int'l Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-7, April 2021. (Acceptance rate = ??%)

[C29] Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu*, and Mango Chao, "Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks," in Proc. of VLSI Test Symposium (VTS), pp. 1-7, April 2021. (Acceptance rate = ??%)

[C28] Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, and Kai-Chiang Wu, "An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention," in Proc. of VLSI Test Symposium (VTS), pp. 1-7, April 2021. (Acceptance rate = ??%)

[C27] Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi-Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, and Mango Chao, "Test Methodology for Defect-based Bridge Faults," in Proc. of Int'l Test Conference in Asia (ITC-Asia), pp. 106-111, Sep. 2020. (Acceptance rate = ??%)

[C26] Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, and Kai-Chiang Wu, "Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator," in Proc. of Int'l Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-3, Aug. 2020. (Acceptance rate = ??%)

[C25] Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu*, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, and Mango Chao, "CNN-based Stochastic Regression for IDDQ Outlier Identification," in Proc. of VLSI Test Symposium (VTS), pp. 1-6, April 2020. (Acceptance rate = ??%)

[C24] Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu*, and Yu-Guang Chen, "Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience," in Proc. of Int'l Symposium on Physical Design (ISPD), pp. 95-102, March 2020. (Acceptance rate = ??%)

[C23] Yu-Teng Nien, Kai-Chiang Wu*, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, and Mango Chao, "Methodology of Generating Timing-Slack-Based Cell-Aware Tests," in Proc. of Int'l Test Conference (ITC), pp. 1-10, Nov. 2019. (Acceptance rate = ??%)

[C22] Ning-Chi Huang, Yu-Guang Chen, and Kai-Chiang Wu, "Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs," in Proc. of IEEE Symposium on VLSI (ISVLSI), pp. 218-223, July 2019. (Acceptance rate = ??%)

[C21] Kai-Chiang Wu*, Wei-Tao Huang, and Chiao-Yang Huang, "ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience," in Proc. of Int'l Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 263-268, July 2019. (Acceptance rate = ??%)

[C20] Tse-Wei Wu, Dong-Zhen Lee, Kai-Chiang Wu*, Yu-Hao Huang, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, and Mango Chao, "Layout-Based Dual-Cell-Aware Tests," in Proc. of VLSI Test Symposium (VTS), pp. 1-6, April 2019. (Acceptance rate = ??%)

[C19] Ning-Chi Huang, Szu-Ying Chen, and Kai-Chiang Wu, "Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 692-697, March 2019. (Regular Paper, Acceptance rate = 24%)

[C18] Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, and Shih-Chieh Chang, "Aging-Aware Chip Health Prediction Adopting an Innovative Monitoring Strategy," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 179-184, Jan. 2019. (Acceptance rate = 35%)

[C17] Tien-Hung Tseng, Shou-Chun Li, and Kai-Chiang Wu, "Lifetime Reliability Trojan based on Exploring Malicious Aging," in Proc. of Asian Test Symposium (ATS), pp. 74-79, Oct. 2018. (Acceptance rate = 51%)

[C16] Kai-Chiang Wu*, Tien-Hung Tseng, and Shou-Chun Li, "MAUI: Making Aging Useful, Intentionally," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 527-532, March 2018. (Regular Paper, Acceptance rate = 24%)

[C15] Tien-Hung Tseng, Shu-Sheng Wang, Jian-You Chen, and Kai-Chiang Wu, "Workload-Aware Lifetime Trojan based on Statistical Aging Manipulation," in Proc. of IEEE Conference on Dependable and Secure Computing (DSC), pp. 159-165, Aug. 2017. (Acceptance rate = 38%)

[C14] Kao-Chi Lee, Kai-Chiang Wu*, Chih-Ying Tsai, and Mango Chao, "Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators," in Proc. of VLSI Test Symposium (VTS), pp. 1-6, April 2017. (Best Paper Nominee)

[C13] Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, and Kai-Chiang Wu, "Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 1219-1224, March 2017. (Regular Paper, Acceptance rate = 24%)

[C12] Chiao-Yang Huang, Chang-Lin Tsai, and Kai-Chiang Wu*, "SAT-Based Time Borrowing against Aging-Induced Timing Errors," in Design Automation Conference Work-in-Progress Session, June 2016.

[C11] Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, and Shih-Chieh Chang, "Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 1269-1274, March 2012. (Regular Paper, Acceptance rate = ??%) [pdf]

[C10] Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, and Shih-Chieh Chang, "Analysis and Mitigation of NBTI-Induced Performance Degradation for Power-Gated Circuits," in Proc. of Int'l Symposium on Low Power Electronics and Design (ISLPED), pp. 139-144, Aug. 2011. (Acceptance rate = 34%) [pdf]

[C09] Kai-Chiang Wu and Diana Marculescu, "Aging-Aware Timing Analysis and Optimization Considering Path Sensitization," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 1572-1577, March 2011. (Regular Paper, Acceptance rate = 27%) [pdf]

[C08] Kai-Chiang Wu and Diana Marculescu, "Clock Skew Scheduling for Soft-Error-Tolerant Sequential Circuits," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 717-722, March 2010. (Regular Paper, Acceptance rate = 27%) [pdf]

[C07] Kai-Chiang Wu and Diana Marculescu, "Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation," in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 75-80, April 2009. (Regular Paper, Acceptance rate = 27%) [pdf]

[C06] Natasa Miskov-Zivanov, Kai-Chiang Wu, and Diana Marculescu, "Process Variability-Aware Transient Fault Modeling and Analysis," in Proc. of Int'l Conference on Computer-Aided Design (ICCAD), pp. 685-690, Nov. 2008. (Acceptance rate = 27%) [pdf]

[C05] Kai-Chiang Wu and Diana Marculescu, "Power-Aware Soft Error Hardening via Selective Voltage Scaling," in Proc. of Int'l Conference on Computer Design (ICCD), pp. 301-306, Oct. 2008. (Acceptance rate = 34%, Best Paper Award) [pdf]

[C04] Kai-Chiang Wu and Diana Marculescu, "Soft Error Rate Reduction Using Redundancy Addition and Removal," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 559-564, Jan. 2008. (Acceptance rate = 29%) [pdf]

[C03] Kai-Chiang Wu, Cheng-Tao Hsieh, and Shih-Chieh Chang, "Delay Variation Tolerance for Domino Circuits," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 354-359, Jan. 2006. (Acceptance rate = 31%) [pdf]

[C02] Cheng-Tao Hsieh, Kai-Chiang Wu, and Shih-Chieh Chang, "Redundancy Addition for Tolerating Delay Variance," in VLSI Design/CAD Symposium (Domestic), Aug. 2004.

[C01] Shih-Chieh Chang, Cheng-Tao Hsieh, and Kai-Chiang Wu, "Re-synthesis for Delay Variation Tolerance," in Proc. of Design Automation Conference (DAC), pp. 814-819, June 2004. (Acceptance rate = 21%) [pdf]

Talks & Posters

Invited Talk at Realtek: Approximate Computing for High-Performance, Energy-Efficient AI at the Edge, Aug. 2019.
Invited Talk at DATE Workshop (on Machine Learning for CAD): Learning-based Methodology for Assessing Chip Health in terms of Aging and Reliability, March 2019. [link]
Seminar at CS, NCTU: Accelerating AI Applications based on High-Performance, High-Accuracy Approximate Computing, Feb. 2019.
Invited Talk at Taiwan AI Academy: Accelerating AI Applications based on High-Performance, High-Accuracy Approximate Computing, Oct. 2018.
Invited Talk at Novatek: Accelerating AI Applications based on High-Performance, High-Accuracy Approximate Computing, Sep. 2018.
Invited Talk at AI Computing Workshop: Accelerating AI Applications based on High-Performance, High-Accuracy Approximate Computing, July 2018. [video]
Seminar at CS, CCU: Addressing IC/SOC Aging: Design-time vs. Run-time, May 2018.
Invited Talk at Realtek: Computer-Aided IC Design for Reliability: Verification and Optimization, Feb. 2018.
Invited Talk at Synopsys: Chip Health Assessment Using Learning-based Monitoring Strategy, Sep. 2017.
Seminar at ICE, CYCU: Reliable and Trustworthy Computing - An IC/CAD Perspective, May 2016.
Seminar at CSIE, NCNU: Reliable and Trustworthy Computing - An IC/CAD Perspective, Jan. 2016.
Seminar at EE, NTU: Computer-Aided IC Design for Reliability: Verification and Optimization, Dec. 2014.
Seminar at CSE, YZU: Computer-Aided IC Design for Reliability: Verification and Optimization, March 2014.
EDA Forum: Analysis and Optimization of Aging-Induced Performance Degradation, Oct. 2013.

Innovation with Impact Research Exhibition: Optimizing Circuit Reliability: From Functional to Temporal Perspectives, Carnegie Mellon University, April 2011.
Ph.D. Forum at DAC 2010: Reducing Circuit Soft Error Rate (SER): From Combinational to Sequential Circuits, June 2010. [pdf]
University Booth at DATE 2010: Reducing Circuit Soft Error Rate (SER): From Combinational to Sequential Circuits, March 2010. [pdf]
CMU CSSI Seminar: On the Mitigation of NBTI-Induced Performance Degradation, Dec. 2009.
CMU CSSI Seminar: Circuit Optimization Techniques for Radiation-Induced Soft Errors, April 2008.

Professional Service

=== After joining NCTU ===

Member

Reviewer

=== Before joining NCTU ===

Reviewer