Symmetric Stream Multi-Processor (SSMP) Architecture

  In this research, we propose a new multicore application processor architecture that facilitates the adoption of the fine-granularity software-pipeline parallelism without causing extra burden on the system bus. The proposed SoC architecture can simultaneously support the traditional symmetric multi-processor (SMP) multi-threading and the proposed software-pipeline applications efficiently. A dedicated pipeline datapath passing through all the processor cores can be used to carry the software-pipeline transactions concurrently with the normal SMP operations. The programming model of the proposed architecture is compatible with the existing SMP operating systems. For the implementation of the pipeline-based parallelism, new programmer-friendly system calls are suggested to take advantage of the new software-pipeline datapath. The proposed architecture with four RISC cores is implemented on an FPGA development board for verification. An AVC/H.264 baseline profile video decoder that explores the pipeline parallelism is implemented on the target platform to justify the benefits of the proposed architecture. Experimental results show that the adoption of the proposed pipeline datapath architecture into existing application processors enables new potentials in exploring software parallelism.


Reference:

Souce code and test data:
    The source code of the parallel video decoders and the hardware platform can be downloaded from here. The source code package is a Xilinx XPS/SDK 13.4 plarform directory. If you have these EDA tools installed, simply double-click the system.xps file in the main directory will open the XPS platform.

    For the parallel video decoders, it is a little bit tricker. We have included three parallel video decoders in the 'workspace' directory. Each decoder occupies one directory as follows:

    1. dynamic_pipeline_skip/ - contains the dynamic software pipeline decoder
    2. single_core/ - contains the baseline single-core decoder
    3. wavefront_one_frame/ - contains the wavefron parallel video decoder


    To build each decoder, you must launch the Xilinx SDK, and open the correpsonding directory under the 'workspace' directory as the SDK workspace directory. Note that, there is an elfcheck error after the SDK generates the elf file. The elf file still works correctly. We will look into the cause of this warning later.

    The video test sequences can be downloaded from here. You must put the test data on the root directory of the Compact Flash card of your XUPV5LX110T development board.

Note:
    Current source code release assumes that you are familiar with the Xilinx ISE Design Suite tools. We apologize that we do not have a tutorial to guide you through the synthesis/compilation of the HW-SW platform step-by-step right now. I do plan to type out a tutorial this summer to help you setup your own platform and give you more insights into the SSMP system hardware and software design. Please be patient ;)

cjtsai@cs.nctu.edu.tw (June. 24, 2014)