Image pyramid generator is an important component for many computer vision applications. Most pyramid generators only produce few levels of down-sampled output images from an input image. In this paper, we present the design of an image pyramid generator optimized for FPGAs that can create a pyramid of up to 24 levels of down-sampled resolutions from the input image, with the scaling factors ranging from 8/32 to 31/32. Since image pyramid processing is essential to many coarse-to-fine solutions of computer vision problems, an image pyramid with more resolution levels can potentially lead to better accuracy for estimation/recognition problems. Furthermore, the down-sampling filters used in the proposed design is based on the Sine-windowed Sinc function filter. Therefore, it preserves more image details than popular low complexity filters such as the bilinear or bicubic interpolation filters. To maintain application flexibility, a HW-SW codesigned approach is adopted so that the granularity levels can be chosen flexibly. The proposed circuit is verified on an FPGA development board with a Xilinx Kintex-7 device. The experimental results show that the design is very promising for real-time computer vision applications.