JAIP - Java Application IP for Embedded SoC


Java Processor IP Design for Embedded SoC

  In this work, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. Secondly, we propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented using a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.

Reference:
Unpublished test programs:
 - Pi.
 - Logic.
 - Java exception test case one.
 - Java exception test case two.

For the JemBench Benchmark Suite, please download it from here.

Hardwiring the OS Kernel into a Java Application Processor

   Now, JAIP has lifted the dependency on a RISC processor, and the JAIP SoC implements the complete funcitons of the Operating System kernels in hardware circuits. The hardwired system functions in the proposed SoC include the thread manager, the memory manager, and the I/O subsystem interface. There are many advantages in making the OS kernel a hardware component, such as a fast system boot time, highly efficient single-core multi-thread context-switching performance, and a better potential for supporting a complex multi-level memory subsystem. In addition, since the target application processor used in this paper is based on Java processor, the system is not susceptible to the stack and pointer-based security attacks that are common to the registerbased processors.

Reference:


cjtsai@cs.nctu.edu.tw (July 12, 2017)